Heretofore, as this type of D-VTR, there is one shown in FIG. 1. In FIG. 1, 1 generally denotes the D-VTR. A digital video signal S1 (FIG. 2(B)) input from a predetermined video signal generating unit is input to a DCT shuffling circuit 2. The DCT shuffling circuit 2 has a DCT address circuit 3 in association therewith, a vertical synchronizing signal SV (FIG. 2(A)) is input to the DCT address circuit 3.
Accordingly, the DCT shuffling circuit 2 divides the digital video signal S1 into DCT blocks of 8 columns x 4 rows for each one field by shuffle address generated by the DCT address circuit 3 on the basis of the vertical synchronizing signal SV. The DCT shuffling circuit 2 collects 10 blocks of the DCT blocks from their respective positions discretely located from each other within a screen to generate shuffle data S2 (FIG. 2(C)), and outputs the shuffle data s2 to the follow ing DCT conversion circuit 4.
Here, the DCT shuffling circuit 2 performs shuffling processing by each one field. Thereby, the shuffle data S2 output from the DCT shuffling circuit 2 is supplied to the DCT conversion circuit 4 at a timing delayed by one field time period T2 from the digital video signal S1 as shown in FIG. 2(C).
The DCT conversion circuit 4 performs discrete cosine transform to data of each DCT block and supplies DCT data S3 to a quantization delay circuit 5 and a quantization level detecting circuit 6. The quantization level detecting circuit 6 detects a quantization level (quantization width) for achieving a target compression rate for the DCT data S3. Since, at this time, about ten-block time period is required as the signal processing time in the quantization level detecting circuit 6, the quantization delay circuit 5 delays the DCT data S3 by the signal processing time, and supplies it to a quantization circuit 7 as a quantization delay output data S5. Accordingly, the quantization delay output data S5 is input to the quantization circuit 7 at the same timing as quantization level data S4 which is output from the quantization level detecting circuit 6 at a time point t3 delayed by a 10-block time period T3 from the shuffle data S2 as shown in FIG. 2(D).
The quantization circuit 7 quantizes the quantization delay output data S5 supplied from the quantization delay circuit 5 based on the quantization level data S4 supplied from the quantization level detecting circuit 6 in order to compress amount of information thereof. At this time, the quantization circuit 7 detects a maximum value, a minimum value, and a mean value etc., of quantization level within one field, on the basis of a period signal for each one field obtained from the vertical synchronizing signal SV at a vertical counter 8 provided in association therewith, and outputs the result as detection data S6 to a quantization monitor (not shown) to monitor the state of compression of data at the quantization circuit 7.
Further, quantization data S7 obtained from the quantization circuit 7 is supplied to a variable-length coding circuit 9. The variable-length coding circuit 9 performs variable-length coding to the quantization data S7 to generate variable-length coding data S9 having a block length prescribed in a format, and outputs it to an error correcting outer coding circuit 11.
The error correcting outer coding circuit 11 generates an error correcting outer code for correcting an error occurred in the manner of a burst, on the basis of a timing obtained from the vertical synchronizing signal SV at a parity timing circuit 12 which is provided in association therewith, and the result is added to the variable-length coding data S9 and is output to a track shuffling circuit 13.
The track shuffling circuit 13 generates track shuffle data S13 by recording the data into an order suitable for the track pattern on a magnetic tape, in accordance with shuffle address obtained from the vertical synchronizing signal SV at a track address circuit 14 which is provided in association therewith.
The track shuffle data S13 is supplied to an error correcting inner coding circuit 15. The error correcting inner coding circuit 15 generates an error correcting inner code for correcting random error and adds to the track shuffle data S13. An ID counter 16 which is provided in association with the error correcting inner coding circuit 15, obtains a block number obtained from the vertical synchronizing signal SV and the color field signal SC, and color field information corresponding to a time period when the phase shift of carrier resulting from phase shifts by each scanning line completes a cycle.
The error correcting inner coding circuit 15 adds the block number and the color field information to the track shuffle data S13 as ID information, and outputs the result to a recording circuit 17 as recording data S12. The recording circuit 17 converts the recording data S12 from an 8 [bit] parallel form to 1 [bit] serial form and effects channel coding suitable for magnetic recording, and records on a magnetic tape 19 by means of a magnetic head 18 provided on a rotary drum.
Here, since the track shuffling circuit 13 performs re-ordering processing of data by each ⅓ field, the recording data S12 obtained on the basis of the track shuffle data S13 is output from the error correcting inner coding circuit 15 at a time point t4 delayed by ⅓ field period T4 from quantization delay output data S5 output from the quantization delay circuit 5 as shown in FIG. 2(E).
Here, in the recording data S12 in the D-VTR 1, a synchronizing pattern is added to the beginning of a data block as a delimiter for the block and a delimiter for restoring data recorded in 1 [bit] serial form on the magnetic tape into the original 8 [bit] parallel form.
Further, a block number for indicating the sequential order of each data block is added as ID information at the error correcting inner coding circuit 15, so that an image is reproduced even when data blocks are not continuously reproduced as the reproducing head helically scans a plurality of tracks in double-speed reproducing etc. Furthermore, color field information is also added as ID information at the error correcting inner coding circuit 15.
Further, video data generated through the above DCT shuffling circuit 2 to the error correcting inner coding circuit 15 is recorded subsequently to the ID information. At the beginning of the video data, the quantization level information in data compression is added at the quantization circuit 7 in accordance with the quantization level data S4. Furthermore, an inner parity data for correcting a random error is added at the error correcting inner coding circuit 15.
In the D-VTR 1 of such construction, data is output with a delay of the time necessary for the signal processing at each signal processing circuit. For example, at the DCT shuffling circuit 2, data is output with a delay corresponding to one field time period T2 (FIG. 2(C)), and at the quantization delay circuit 5, data is delayed by 10-block time period T3 (FIG. 2(D)). Further, at the DCT conversion circuit 4, the quantization circuit 7, and the variable-length coding circuit 9, data is delayed by about one block time period respectively, and at the track shuffling circuit 13, data is delayed by ⅓ field time period T4 (FIG. 2(E)).
Accordingly, at the timing circuits of the vertical counter 8, the parity timing circuit 12, the track address circuit 14, and the ID counter 16, timing signals must be generated with their phase conforming to their respective delay time from the vertical synchronizing signal SV.
Further, while the color field information is input at the same timing as the digital video signal S1, data (track shuffle data S13) input to the error correcting inner coding circuit 15 to which the color field information is to be added as ID information is delayed by about 1.4 field from the input point t1 (FIGS. 2(A) to 2(E)) of the digital video signal S1. Accordingly, a latch circuit for reading the color field information with a delay corresponding to such delay time is necessary at the ID counter 16, resulting in a problem of complicating the construction.
Further, all of these delay phases occur as an accumulation of processing time in the signal processing circuits up to the previous stage of that point and, when processing time of a signal processing circuit is changed in its development process, timing of all the signal processing circuits after the changed signal processing circuit must be corrected in accordance with such changed time period.